錯的優

module top;
wire [2:0]A,B,OUT;
wire SEL;
system_clock #6400 clock1(A[2]);
system_clock #3200 clock2(A[1]);
system_clock #1600 clock3(A[0]);
system_clock #800 clock4(B[2]);
system_clock #400 clock5(B[1]);
system_clock #200 clock6(B[0]);
system_clock #100 clock7(SEL);
mux3 M1(OUT, A, B, SEL);
endmodule

module mux3(OUT, A, B, SEL);
 output OUT;
 input [2:0]A,B;
 input SEL;
 wire  [2:0]A,B;
 wire  SEL;
 reg   [2:0]OUT;

  always @(A[0] or A[1] or A[2] or B[0] or B[1] or B[2] or SEL)
   begin
   OUT = (A[0] & SEL)|(B[0] & ~SEL );
   OUT = (A[1] & SEL)|(B[1] & ~SEL );
   OUT = (A[2] & SEL)|(B[2] & ~SEL );
   end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>7000)$stop;

endmodule